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MV8870/MV8870-1
ADVANCE INFORMATION
DS3140-2.1
MV8870 / MV8870-1
INTEGRATED DTMF RECEIVER
The MV8870 / MV8870-1 is a complete DTMF receiver integrating both the bandsplit filter and digital decoder functions, fabricated in GPS's double-poly ISO2-CMOS technology. The filter section uses switched capacitor techniques for high and low group filters; the decoder uses digital counting techniques to detect and decode all 16 DTMF tone pairs into a 4-bit code. External component count is minimised by on-chip provision of a differential input amplifier, clock oscillator and latched 3-state bus interface. The MV8870 and MV8870-1 are functionally identical, but differ in Electrical Characteristics.
IN+ INGS VREF SEL PD OSC1 OSC2 VSS
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE
DG18 DP18 MP18
27 St/GT
28 VDD
s s s s s
Complete DTMF Receiver Low Power Consumption Internal Gain Setting Amplifier Adjustable Guard Time Central Office Quality
26 ESt 25 StD 24 NC 23 NC 22 FLT 21 FL 20 Q4 19 Q3 Q2 18
VREF 5 NC 6 SEL 7 FHT 8 FH 9 PD 10 NC 11 OSC1 12 OSC2 13 VSS 14 NC 15 TOE 16 Q1 17
APPLICATIONS
s s s s s Receiver Systems for BT or CEPT Specifications Paging Sytems Repeater Systems / Mobile Radio Credit Card Systems Remote Control
1 IN+
FEATURES
3 GS 4 NC 2 IN-
HP28
Figure 1: Pin connections - top view
SEL 5(7) PD FHT (8) FH (9) 11(17) Q1
6(10)
HIGH GROUP FILTER
IN+ INGS 1(1) 2(2) 3(3) 12(18) ZERO CROSSING DETECTORS
DIAL TONE FILTER
DIGITAL DETECTION ALGORITHM
CODE CONVERTER AND LATCH
Q2
13(19)
Q3
LOW GROUP FILTER
CHIP CHIP POWER BIAS
14(20)
Q4
10(16) CHIP CLOCKS 4(5) VREF (22) 7(12) OSC1 8(13) OSC2 (21) FL
TOE
BIAS CIRCUIT
18(28) 9(14) VSS
STEERING LOGIC
16(26) ESt
15(25) StD
17(27) St/GT
VDD
FLT
Figure 2: Functional block diagram (Pin numbers in brackets refer to HP package)
1
MV8870/MV8870-1
FUNCTIONAL DESCRIPTION
The MV8870 / MV8870-1 monolithic DTMF receiver offers small size, low power consumption and high performance. Its architecture consists of a bandsplit filter section, which separates the high and low tone groups, followed by a digital counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. FILTER SECTION Separation of the low-group and high-group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor band-pass filters, the bandwidths of which correspond to the low and high group frequencies. The filter section also incorporates notches at 350 and 440 Hz for exceptional dial tone rejection (see Fig.3). Each filter is followed by a single order switched capacitor filter section which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the trequencies of the incoming DTMF signals. For testing and monitoring, the high and low group filter and zero crossing detector outputs are made available via FHT, FH, FLT and FL (HP package only). DECODER SECTION Following the filter section is a decoder employing digital counting techniques to determine the frequencies ot the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognises the simultaneous presence of two valid tones (this is referred to as the `Signal Condition' in some industry specifications) the Early Steering output (ESt) will go to an active state. Any subsequent loss of signal condition will cause the ESt pin to go to its inactive state (see Fig.5).
X 0 Y ABC D
STEERING CIRCUIT Before registration of a decoded tone-pair, the receiver checks for a valid signal duration (referred to as (character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes the voltage at the SVGT pin (VSt/GT) to rise as the capacitor discharges (see Figs.4 and 5). Provided signal condition is maintained (ESt remains high) for the validation period (tGTP), VSUGT reaches the threshold (VTSt) of the steering logic which allows it to register the tone pair and strobe the corresponding 4-bit code into the output latch (see Fig.6). At this point the SVGT pin is activated as an output and drives VSt/GT to VDD (see Fig.5). St/GT continues to drive high as long as ESt remains high. After a short delay (tDP) to allow the output latch to settle, the delayed steering output pin (StD) goes high to indicate that the code for a new received tone-pair is available. The contents of the output latch are output onto the output bus (Q1 to Q4 pins) when the three-state output enable (TOE) pin is high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (drop-out) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.
VDD C VDD MV8870/ MV8870-1 St/GT ESt StD 18 17 16 15 R
tGTA = RC In {VDD / VTSI} tGTP = RC In {VDD / (VDD - VTSU)}
Figure 4: Basic Steering Circuit
E F G H Precise Dial Tones X = 350 Hz Y = 440 Hz DTMF Tones A = 697 Hz B = 770 Hz C = 852 Hz D = 941 Hz E = 1209 Hz F = 1336 Hz G = 1477 Hz H = 1633 Hz
10
20 ATTENUATION (dB) 30
40
50
200
400
600
800
1000
1200
1400
1600
1800
2000
FREQUENCY (Hz)
2
Figure 3: Filter response
MV8870/MV8870-1
APPLICATIONS
A simple application circuit is shown in Fig.7. This has a symmetric guard time circuit, a single-ended analog input and a dedicated crystal oscillator. GUARD TIME ADJUSTMENT In many situations not requiring seperate selection of tone duration and interdigit pause, the simple steering circuit shown in Fig.7 is applicable. Component values are chosen according to the formulae (see Figs. 4, 8a and 8b):tREC = tDP + tGTP tlD = tDA + tGTA The value of tDP is a device parameter (see Dynamic Characteristics and Fig.5) and tREC is the minimum signal duration to be recognised by the receiver. Likewise tDA is a device parameter (Fig.5) and tlD is the minimum time taken to recognise an interdigit pause. A value for C2 of 0.1-F is recommended for most applications, leaving R3 to be selected by the designer. Different steering arrangements may be used to select independantly the guard times for tone present (tGTP) and tone absent (tGTA). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigit pause. Guard Time adjustment also allows the designer to tailor system parameters such as talk-off and noise immunity. Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will maintain signal conditions long enough to be registered. Alternatively a relatively short tREC wim a long tlD would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figs. 8a and 8b.
A
B
C
E
F
G
VIN tDA ESt tDP tDP VTSt St/GT tDA tDP
TONE N tDA tDP
TONE N + 1 tDA
TONE N + 1 tDP tDA
t < tGTP StD CODE CONVERTER LATCH OUTPUTS TOE
t < tGTP
t = tGTP
t = tGTA
t = tGTP
t < tGTA
t = tGTA
tPStD DECODED TONE N-1
tPStD TONE N
tPStD TONE N + 1
tPStD
tPQ
tPQ
Q1 - Q4 D
TONE N D
TONE N + 1 D
EXPLANATION OF EVENTS A, Tone bursts detected, but tone duration invalid and output latch unchanged. B. Tone N detected, tone duration valid, output latch updated and new data signalled by StD. C. End of tone N detected, tone absent duration valid, but output latch updated until next valid tone. D. Outputs switched to high impedance. E. Tone N + 1 detected, tone duration valid, tone decoded, output latch updated (although outputs are currently high impedance) and new data signalled by StD. F. Acceptable dropout of tone N + 1, tone absent duration invalid, StD and output latch unchanged. G. End of tone N + 1 detected, tone absent duration valid, StD goes low but output latch not updated until next valid tone.
NOTES 1. tDP time for valid tone present is a device parameter (see Electrical Characteristics). 2. tDA time for valid tone absent is a device parameter (see Electrical Characteristics). 3. tGTP and tGTA are adjustable via external RC network at pins 16 and 17 (see Fig. 4). 4. tPSID and tPQ are propogation delays given in Electrical Characteristics.
Figure 5: Timing diagram
3
MV8870/MV8870-1
fLOW 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 fHIGH 1209 1336 1477 1209 1336 1477 1209 1336 1477 1209 1336 1477 1633 1633 1633 1633 DIGIT TOE Q4 1 2 3 4 5 6 7 8 9 0 * # A B C D Any H H H H H H H H H H H H H H H H L 0 0 0 0 0 0 0 1 1 1 1 i 1 1 1 0 Z SELECT = L Q3 0 0 0 1 1 1 1 0 0 0 0 1 1 1 l 0 Z Q2 0 1 1 0 0 1 1 0 0 1 1 0 0 1 l 0 Z Q1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z Q4 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 Z SELECT = H Q3 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 Z Q2 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 Z Q1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 Z
Figure 6: Functional decode table
VDD MV8870/ MV8870-1
1 2
DTMF OUTPUT
IN+ INGS VREF SEL PD OSC1 OSC2 VSS
VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE
18 17 16 15 14 13 12 11 10
C2
3
C1 R1 R2
R3
4 5 6
R1, R2 = 100k1% R3 = 300k1% C1, C2 = 0.1F5% X = 3.579545MHz0.1% X
7 8 9
}
VDD 18 17 16 15 St/GT ESt
DECODED OUTPUT
Figure 7: Simple application circuit; single ended input
VDD C 18 17 16 15 StD R2 StD R1 MV8870/ MV8870-1 VDD C
VDD MV8870/ MV8870-1 St/GT ESt
R1
R2
tGTA = R1C In {VDD / VTSt} tGTP = RPC In {VDD / [VDD - VTSt]} RP = R1R2 / {R1 + R2}
tGTA = RPC In {VDD / VTSt} tGTP = R1C In {VDD / [VDD - VTSt]} RP = R1R2 / {R1 + R2}
Figure 8a: Guard time adjustment (tGTP < tGTA)
Figure 8b: Guard time adjustment (tGTP > tGTA)
4
MV8870/MV8870-1
DIFFERENTIAL INPUT CONFIGURATION The input arrangement of the MV8870 / MV8870-1 provides a differential input op. amp. and a bias source (VREF) to bias the inputs at mid-rail. The gain may be adjusted through a feedback resistor from the op. amp. output (GS). In a singleended configuration the input pins are connected as shown in Fig. 7 where the op. amp. is connected to give unity gain and the VREF pin biases the input at (VDD / 2). Fig.9 shows the differential configuration. In this circuit gain is adjusted through the feedback resistor R5. CRYSTAL OSCILLATOR The internal clock circuit is completed with the addition of an external 3.58MHz crystal which is normally connected as shown in Fig. 7. However it is possible to configure several MV8870 / MV8870-1 devices to use only a single oscillator crystal. The devices are chained together with the oscillator output of the first device in the chain capacitively coupled to the oscillator input of the second device and so on down the chain. The details are shown in Fig. 10. Precision balancing capacitors are not required as problems of unbalanced loading are not a concern. RECEIVER SYSTEM FOR BT SPECIFICATION POR 1151 The circuit shown in Fig.11 illustrates the use of the MV8870-1 in a typical receiver system. The BT specification defines the non-operate level as input signals below 34 dBm. This is obtained by choosing R1 and R2 to give 3dB of attenuation so that an input of 34 dBm corresponds to -37 dBm at the op. amp. output pin (GS). The tolerances on R3 and C2 give a tolerance on guard time of 6%. For better performance the non-symmetric guard time circuit shown in Fig.12 is recommended.
C1
C2
DTMF INPUT
C1
VDD MV8870/ MV8870-1
R1
R4 1 2 R5 3 IN+ INGS MV8870/ MV8870-1 4 VREF
X R1
+ R2
1 2 3 4 5 6 7 8 9
IN+ INGS VREF SEL PD OSC1 OSC2 VSS
VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE
18 17 16 15 14 13 12 11 10
C2
R3
R3
R2
}
DECODED OUTPUT
Differential Input Amplifier C1 = C2 = 0.01F Resistors are 1% R1 = R4 = R5 = 100k R2 = 60k Capacitors are 5% R3 = R2R5 / (R2 + R5) Voltage Gain (AVdiff) = R5 / R1 Input Impedance ZINDIFF = 2[R12 + (1 / wC)2]1/2
R1 = 102k 1% R2 = 71.5k 1% R3 = 390k 1% C1, C2 = 0.1F 5% X = 3.579545MHz 0.1%
Figure 9: Differential input configuration
MV8870/ MV8870-1 OSC1 OSC2 7 8 X C C 7 8 MV8870/ MV8870-1 OSC1 OSC2
Figure 11: Single ended circuit for BT/CEPT Specs
VDD C 18 17 16 15 StD R2 R1
VDD MV8870/ MV8870-1 St/GT ESt
C = 30pF X = 3.57945MHz
To OSC1 of next MV8870/ MV8870-1
tGTA = R1C In {VDD / VTSt} tGTP = RPC In {VDD / [VDD - VTSt]} RP = R1R2 / {R1 + R2}
R1 = 368k 1% R2 = 2.2m 1% C = 0.1F 5%
Figure 10: Oscillator circuit
Figure 12: Non-symmetric guard time circuit
5
MV8870/MV8870-1
PIN DESCRIPTIONS (Note 1) Symbol IN+, IN GS VREF SEL PD FHT FH OSC1 Pin no 1 (1) 2 (2) 3 (3) 4 (5) 5 (7) 6 (10) - (8) - (9) 7 (12) Pin name and description In Plus and Minus (Voltage Inputs). These are respectively the non-inverting and inverting inputs to the front-end op-amp. The DTMF input is applied to these pins in normal operation. Gain Select (Voltage Output). This pin is connected to the output of the front-end op-amp. A feedback resistor between this pin and the inverting input (IN - ) controls the front-end gain. Reference Voltage (Voltage Output). This pin outputs a voltage which is half-way between the power supply voltages (VSS and VDD). It can be used to bias the input signal. Select Input. This pin determines the Q4........Q1 truth table as shown in Fig. 6 Power Down Input. This pin is used to power down and inhibit the oscillator. It is active high and includes an internal pull-up resistor. Fllter High Tones. Sine wave output from the high group filter circuit. High Frequency OutpuL Square wave output from the high group zero crossing detector. Oscillator 1 (Digltal Input). This is the input to the inverter of the oscillator circuit. There is an internal biasing resistor between this pin and the inverter output (OSC2). A 3.579545MHz crystal is normally connected externally between the two pins to complete the oscillator circuit. Oscillator 2 (Digital Output). This is the output of the inverter of the oscillator circuit. There is an internal biasing resistor between this pin and the inverter input (OSC1). A 3.579545MHz crystal is normally connected externally between the two pins to complete the oscillator circuit. Negative Supply (Power Input). This is the negative power supply for the device. It is normally 0V. Three-State Output Enable (Digital Input with Pull-up). If this pin is high then the decoder outputs (Q1 to Q4) are enabled. If it is low then the outputs go into their high-impedance state. There is an internal pull-up at this pin. Q1 to Q4 (Three-State Outputs). When the TOE pin is high these pins output the code in the output latch which corresponds to the last valid tone-pair detected. They go into their high impedance state when the TOE pin is low. Low Frequency Output. Square wave output from the low group zero crossing detector Filter Low Tones. Sine wave output from the low group filter circuit. Delayed Steering (Digital Output). This pin follows the ESt and SVGT pins. It goes high to indicate that a new tone-pair has been detected and the corresponding code has been loaded into the output latch. It goes low to indicate that a new tone-pair is expected. Early Steerlng (Digital Output). This pin goes high when the digital detection algorithm decides that there is a valid DTMF input. It goes low as soon as the algorithm decides that there is no valid DTMF input. In normal use this pin is used to drive an external guard time circuit which in turn drives the SUGT pin. Steerlng / Guard Time (Voltage Input / Digltal Output). This pin follows the ESt pin. When ESt pin changes state this pin acts as an input and monitors the voltage developed here by the ESt pin acting through the external guard time circuit. When the voltage reaches the internally generated VTSI level then this pin acts as an output and pulls itself fully to the state of the ESt pin. When this pin goes fully high a new code is loaded into the output latch and the StD pin goes high. When this pin goes fully low the device prepares itself for a new tone-pair and the StD pin goes low. Positive Supply (Power Input). This is the positive power supply for the device. It is normally 5V.
OSC2
8 (13)
VSS TOE
9 (14) 10 (16)
Q1 Q2 Q3 Q4 FL FLT StD
11 (17) 12 (18) 13 (19) 14 (20) - (21) - (22) 15 (25)
ESt
16 (26)
SVGT
17 (27)
VDD
18 (28)
Note: 1. Figures in brackets are for HP28 package.
6
MV8870/MV8870-1
RECOMMENDED OPERATING RANGE
Value (MV8870) Characteristic Positive supply voltage Operating temperature Symbol VDD TOP Min 4.75 -40 Typ 5.0 +25 Max 5.25 +80 Value (MV8870-1) Min 4.75 -40 Typ 5.0 +25 Max 5.25 +80 Units V C Conditions
ELECTRICAL CHARACTERISTICS Over Recommended Operating Range (unless otherwise specified)
These characteristics are guaranteed over the following conditions (unless otherwise stated): Voltages measured with respect to ground (VSS). Typical figures are for design aid only; they are not guaranteed and are not subject to production testing. STATIC CHARACTERISTICS Value (MV8870) Characterlstlc Symbol Min Power dissipation VDD supply current Input high voltage (OSC1 & Input low voltage (OSC1 and TOE) Input leakage current (OSC1, IN + and IN-) Internal pull-up current (TOE) Steering threshold voltage (St/GT) Low level output voltage High level output voltage PD IDD VIH VIL 3.5 0 Typ 15 3.0 Max 35 7.0 VDD 1.5 3.5 0 Mln Typ 15 3.0 Max 37 7.0 VDD 1.5 mW mA V V 0 VPIN VDD 0 VPIN VDD f0 = 3.579545MHZ Value (MV8870-1) Unlts Conditions
ll
100
100
mA A V
IPU VTSt 2.2
7.5 2.35
15.0 2.5 2.2
7.5 2.35
15.0 2.5
VOL VOH 1.0
0.03 4.97 2.5 1.0
0.03 4.97 2.5
V V mA
No Load No Load VPIN = 0.4V
Output low sink current (OSC2, IOL Q1-Q4, StD and ESt) Output high source current (OSC2, Q1-Q4, StD and ESt) Reference voltage VREF output resistance Pin capacitance IOH
0.4
0.8
0.4
0.8
mA
VPIN = 4.6V
VREF RREF CP
2.4 10.0 7.0
2.7
2.4 10.0
2.8
V k
No Load
15.0
7.0
15.0
pF
Pin to supplies
7
MV8870/MV8870-1
DYNAMIC CHARACTERISTICS: INPUT OP AMP Value (MV8870) Characteristic Symbol Min Input impedance (IN+ and IN-) RIN Typ 10 25 100 60 3.0 60 65 1.5 Max Min Typ 10 25 100 60 3.0 60 65 1.5 Max M mV nA dB V dB dB MHz ROUT to VSS 100k VSSMV8870-1) Units Conditions
Input offset voltage (IN+ and IN-) VOS Input leakage current Power supply rejection Common mode range Common mode rejection DC open loop voltage gain Open loop unity gain bandwidth Output voltage swing (GS) Output capacitive load (GS) Output resistive load (GS) IIN PSRR VCM CMRP AVOL fC
VO COUT ROUT 50
4.5 100 50
4.5 100
Vp-p pF k
DYNAMIC CHARACTERISTICS: OSCILLATOR CIRCUIT Value (MV8870 and MV8870-1) Characteristic Symbol Min Crystal/clock frequency (OSC1 and OSC2) Oscillator input rise time (OSC1) - external clock Oscillator input high time (OSC1) - external clock Oscillator input fall time (OSC1) - external clock Oscillator Input Low Time (OSC1 Pin) - external clock Oscillator Output Load (OSC2) fO 3.579 Typ 3.579545 Max 3.5831 MHz Units Conditions
tOR
110
ns
See Fig.13
tOH
110
170
ns
See Fig.13
tOF
110
ns
See Fig.13
tOL
110
170
ns
See Fig.13
CLO
30
pF
8
MV8870/MV8870-1
DYNAMIC CHARACTERISTICS: DETECTOR Value (MV8870) Characterslic Symbol Min Valid input level (GS) VVL PVL VlL PIL TAP TAN FA -1.5 -2.0 -5.0 3.5 -16 -12 + 22 5 0.5 11 4.0 14 8.5 5 05 5.0 10 10 6.0 6.0 +1.5 -1.5 + 2.0 -2.0 -3.5 . 3.5 -5.0 5.0 -18 -12 + 22 11 40 14 8.5 10 10 _ +1.5 +2.0 -3.5 _ dB dB dB ms ms 77 7 -29 Typ Max Min Typ Max 2458 10 30.8 -37 mVp-p dBm mVp-p dBm dB dB % Hz % 1, 2, 3, 5, 6, 9 Value (MV8870-1) Units Notes
2458 6-1 7 1.0 -31
Invalid input level (GS)
1, 2, 3, 5, 6. 9
Acceptable positive twist Acceptable negative twist Frequency deviation accept
2, 3, 6, 9 2, 3, 6, 9 2, 3, 5, 9
Frequency deviation rejected as too low FRL Frequency deviation rejected as too high FRH Third tone tolerance Noise tolerance Dial tone tolerance Tone present detect time Tone absent detect time PITT PNT PDTT tDP tDA
2, 3, 5, 9 2, 3, 5, 9 2, 3, 4, 5, 9,12 2, 3, 4, 5, 7, 9, 10 2, 3, 4, 5, 8, 9, 11
NOTES 1. dBm = decibels above or below a reference power of 1 mW into a 600 load. 2. Digit sequence consists of all DTMF tones. 3. Tone duration = 40ms, tone pause = 40ms. 4. Signal condition consists of nominal DTMF frequencies. 5. Both tones in composite signal have equal amplitudes. 6. Tone pair is deviated by (1.5% + 2Hz). 7. Bandwidth limited (3kHz) Gaussian noise. 8. The precise dial tone frequencies are (350Hz and 440Hz) 2%. 9. For an error rate of better than 1 in 10,000. 10. Referenced to lowest frequency component in DTMF signal. 11. Referenced to the minimum valid input level. 12. Refer to Fig.11. Input DTMF Tone Level at - 25dBm (- 28dBm at GS pin). Interference Frequency Range is 480 to 3400Hz. DYNAMIC CHARACTERISTICS: DECODER Value (MV8870/MV8870-1) Characteristic Propagation delay (SVGT to Q) Propagation delay (SVGT to StD) Output data set-up time (Q to StD) Enable propagation delay (TOE to Q) Disable propagation delay (TOE to Q) Symbol Min tPQ tPSID tQSID tPTE tPTD Typ 8 12 3.4 50 300 60 Max 11 s s s ns ns TOE high. See Fig.14 See Fig. 14 TOE high. See Fig.14 RL = 10k(pulldown) CL = 50pF See Fig. 15. RL = 10k(pulldown) CL = 50pF See Fig. 15. Units Conditions
9
MV8870/MV8870-1
tOH
tOL
3.5V OSC1 1.5V tOR tOF
Figure 13: Timing - external oscillator input
St/GT
VTSt tPQ 4.6V
Q1 - Q4
0.4V tQStD 4.6V
StD 0.4V tPStD
Figure 14: Timing - decoded data
3.5V TOE 1.5V tPTE 4.6V Q1 - Q4 0.4V tPTD
Figure 15: Timing - Output enable and disable
ABSOLUTE MAXIMUM RATINGS* Voltages are with respect to the negative power supply (VSS)
Value (MV8870) Parameter Positive supply voltage (Pin 18) Current at any pin (other than supplies) Storage temperature Package power dissipation Symbol . VDD -0.3 -65 IMAX TSTG PP Min Max +6.0 VDD + 0 3 10 +150 1000 -65 -0 3 Value (MV8870-1) Units Mln Max +6.0 VDD + 0 3 10 +150 1000 mA C mW V
Voltage on any pin (other than supplies) VMAX
* Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied. Derate parameter above + 75C at 16mW/C, all leads soldered to board.
10
MV8870/MV8870-1
HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O.Box 660017, 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel (408) 438 2900 Fax: (408) 438 5576
CUSTOMER SERVICE CENTRES * FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07 * GERMANY Munich Tel: (089) 3609 06-0 Fax : (089) 3609 06-55 * ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 * JAPAN Tokyo Tel: (3) 5276-5501 Fax: (3) 5276-5510 * NORTH AMERICA Integrated Circuits and Microwave Products, Scotts Valley, USA Tel (408) 438 2900 Fax: (408) 438 7023. Hybrid Products, Farmingdale, USA Tel (516) 293 8686 Fax: (516) 293 0061. * SOUTH EAST ASIA Singapore Tel: 2919291 Fax: 2916455 * SWEDEN Johanneshov Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 * UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (0793) 518510 Fax : (0793) 518582 These are supported by Agents and Distributors in major countries world-wide. (c) GEC Plessey Semiconductors 1993 Publication No. DS 3140 Issue No. 2.1 September 1993
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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